CDA 3101 Laboratory Exercise No. 2
DUE: Oct. 4, 1995
Sequential Logic Circuits
   I. Using NOR gates, implement two SR flip flops and verify their operation.
      
  
  II. a.     Using the SR flip flops in part I, implement a Master/Slave clocked
             D flip flop.  Verify the operation of the D flip flop.
      b.     Using the M/S SR flip flop, implement a JK flip flop (Master-slave
             clocked).  Verify the operation of the JK flip flop.  
 III. Using the JK flip flop from part IIb, implement a T flip flop.  Again,
      verify the operation of your T flip flop.
  IV. Verify the operation of the D flip flops in a 7474 chip. Also, verify the
      operation of the JK flip flops in a 7476 chip.
   V. Build a MOD 4 counter using a 7476.
  VI. Build a MOD 16 counter using two 7476s.
Document each of the above parts.  Include problem statements, schematic
diagrams (wiring diagrams not required), state diagrams and state transition
tables showing operation of your circuits, narrative on the design and
implementation of your circuits, conclusions.
BE NEAT!           
Your circuits for parts III and VI must be successfully demonstrated to your
instructor or the lab assistant on or before the due date.

DEMO & Signature:
             Part III _______________________   

             Part VI  _______________________