Fall, 2005  . Lab 1: Combinational Logic Circuits Due Date: Wednesday, October 5, 2005 (beginning of class) Reminder: each team member is to conduct or otherwise be involved in the demonstration of your implementation. Using only standard logic gates, design and implement a combinational circuit for the following problem: A device is needed to provide capacity monitoring for a four valve assembly. Each valve is either open or closed. Design and implement a logic circuit that will exhibit a light pattern (red lights): RRRR = all valves are open RRR = exactly 3 of the 4 valves are open RR = exactly 2 of the 4 valves are open R = exactly 1 of the 4 valves is open i.e., the light pattern is determined by how many of the 4 valves are open. Note that the light pattern does not identify which valves are open or closed. Implement the logic function for light #2 (two or more valves open) using a 74151 multiplexer chip. Using the same inputs in parallel with your circuit for part A, attach the output for your 74151 implementation to a 5th light so that you can demonstrate the equivalence of your original circuitry for light #2 with that done using the 74151. Write a report ordered as follows: cover page with group number and team member signatures completed certification page for each team member (attached) concise problem statement stating the purpose of the exercise and how it is to be done equipment explanations: equipment required and carefully explained schematic diagrams as illustrated in the lab supplement of chip layouts (to record how you implemented each part of the lab) technical explanations: for this lab you will need to explain your design, exhibiting and amplifying on truth tables associated with your design; you will be expected to have employed K-map reduction, and possibly additional simplification for part A; you will need to exhibit the logic for setting up the 74151. technical observations: recapitulation - please do not recite your implementation problems except as they lead to discovery; you are experimenting; in this lab, for example, after minimizing using K-maps, were you able to reduce circuit size further by algebraic manipulation? did you have excess gates you couldn't take advantage of? do you think your chip utilization is minimal? did you have design alternatives? (and why did you go the way you did), etc. technical conclusions: observations which allow you to reach definitive conclusions should be concisely summed up; for this lab, the theory predicts substantial circuit size reduction using techniques such as K-maps and algebraic manipulation; it also predicts that a 74151 provides an alternative means for implementing parts of logic circuits; a construction set up for one part of the circuit may provide data which can be used in another. Does your experiment provide support for the theory? Can you make any statement regarding how using a 74151 might hurt as well as help?